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3.1.12
Count Register (COUNT)
The count register is a read-only register which provides the current value of a free-running 8-bit counter derived from the pri-
mary oscillator. A 10-bit pre-scaler divides the primary oscillator frequency by 1024. Thus, the value in the register increases by
one count every 128 μ s and the counter rolls over every 32.768 ms.
Table 23. Count Register
Location
Bit
Address
$15
Register
COUNT
7
COUNT[7]
6
COUNT[6]
5
COUNT[5]
4
COUNT[4]
3
COUNT[3]
2
COUNT[2]
1
COUNT[1]
0
COUNT[0]
Reset Value
0
0
0
0
0
0
0
0
3.1.13
Offset Correction Value Registers (OFFCORR_X, OFFCORR_Y)
The offset correction value registers are read-only registers which contain the most recent offset correction increment / dec-
rement value from the offset cancellation circuit. The values stored in these registers indicate the amount of offset correction be-
ing applied to the SPI output data. The values have a resolution of 1 LSB.
Table 24. Offset Correction Value Register
Location
Bit
Address
Register
7
6
5
4
3
2
1
0
$16
$17
OFFCORR_ OFFCORR_ OFFCORR_ OFFCORR_ OFFCORR_ OFFCORR_ OFFCORR_ OFFCORR_ OFFCORR_
X X[7] X[6] X[5] X[4] X[3] X[2] X[1] X[0]
OFFCORR_ OFFCORR_ OFFCORR_ OFFCORR_ OFFCORR_ OFFCORR_ OFFCORR_ OFFCORR_ OFFCORR_
Y Y[7] Y[6] Y[5] Y[4] Y[3] Y[2] Y[1] Y[0]
Reset Value
0
0
0
0
0
0
0
0
3.1.14
Reserved Registers (Reserved)
Registers $1C and $1D are reserved. A write to the reserved bits must always be logic ‘0’ for normal device operation and
performance.
Table 25. Reserved Registers
Location
Bit
Address
$1C
$1D
Register
Reserved
Reserved
7
Reserved
Reserved
6
Reserved
Reserved
5
Reserved
Reserved
4
Reserved
Reserved
3
Reserved
Reserved
2
Reserved
Reserved
1
Reserved
Reserved
0
Reserved
Reserved
Reset Value
0
0
0
0
0
0
0
0
3.2
3.2.1
Customer Accessible Data Array CRC Verification
OTP Shadow Register Array CRC Verification
The OTP shadow register array is verified for errors using a 3-bit CRC. The CRC verification uses a generator polynomial of
g(x) = X 3 + X + 1, with a seed value = ‘111’. If a CRC error is detected in the OTP array, the IDE bit is set in the DEVSTAT register.
3.2.2
Writable Register CRC Verification
The writable registers in the data array are verified for errors using a 3-bit CRC. The CRC verification is enabled only when
the ENDINIT bit is set in the DEVCFG register. The CRC verification uses a generator polynomial of g(x) = X 3 +X+1, with a seed
value = ‘111’. If a CRC error is detected in the writable register array, the IDE bit is set in the DEVSTAT register.
MMA65xx
Sensor
Freescale Semiconductor, Inc.
21
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